1. Technical Field
Various embodiments relate to a semiconductor circuit, and more particularly, to a synchronization circuit.
2. Related Art
For example, a semiconductor circuit generates an internal clock signal using an externally provided clock signal and outputs data using the internal clock signal.
Since the internal clock signal passes through various signal paths in a semiconductor memory, a timing error occurs between the internal clock signal and the externally provided clock signal.
Therefore, the semiconductor circuit uses a synchronization circuit in order to compensate for the timing error between the externally provided clock signal and the internal clock signal.
As illustrated in FIG. 1, a synchronization circuit 10 according the conventional art, that is, a delay locked loop (DLL) includes a delay line 11, a replica delay 12, a phase detector 13, a control unit 14, and a driver 15.
The delay line 11 delays an input signal ICLK by a variable delay time in response to control signals T0<0:M> and T1<0:N> and outputs a delayed signal.
The replica delay 12 is a delay circuit that duplicates a delay time of a signal path through which the input signal ICLK is output to an outside.
The phase detector 13 detects a phase difference between the input signal ICLK and the output signal of the replica delay 12, and outputs the phase difference.
The control unit 14 generates the control signals T0<0:M> and T1<0:N> to compensate for the phase difference between the input signal ICLK and the output signal of the replica delay 12 according to the output of the phase detector 13.
The driver 15 drives the output signal of the delay line 11 to output a delay locked clock signal DCLK.
As illustrated in FIG. 2, the delay line 11 includes a plurality of NAND gates for receiving the control signals T0<0:M>, and a plurality of unit delay cells (UDCs) for receiving the control signals T1<0:N>.
The number of the unit delay cells through which an input signal IN passes is determined according to the control signals T0<0:M> and T1<0:N>, so that it is possible to change the delay time of the input signal IN.
The synchronization circuit according to the conventional art performs a locking operation (delay locking operation) for adjusting tDL (a delay locking time) to have a minimum positive value in the range of tCK (a clock time)—tREP (a replica delay time).
At this time, when a change occurs in a power supply voltage provided to a semiconductor circuit, for example, when the power supply voltage does not reach a target level, the delay time (tREP) of the replica delay 12 may increase.
When the tREP increases, the tDL may be reduced to a negative value in a locking process.
Since the tDL is not allowed to have a negative value in an actual circuit, delay stuck occurs, resulting in the occurrence of a data output timing error.
Thus the synchronization circuit 10 according to the conventional art is designed such that locking with a tDL corresponding to 2*tCK-tREP is performed.
However, in order to perform the locking with the tDL corresponding to 2*tCK-tREP as described above, a delay line used increases, resulting in an increase in power consumption amount, a locking time, and jitter.